Process for the manufacture of III-V semiconductor devices

ABSTRACT

A process for the manufacture of a transistor device of the type having active regions e.g. an emitter (17) and a base (11) each contacted by isolated extended conductive regions (37, 33) respectively. At start of process a mesa structure is defined in layered III-V material (3, 5, 11 and 13). The sidewall of the mesa is covered by a conformal coating (27) of insulating material; and, lattice matched material (33) grown on the exposed adjacent material (25) to form a first extended contact. This then is covered by a further layer (35) of insulating material (35). The second extended contact (37) is then grown over the mesa active region material (13). This contact material (37) is isolated from the first contact material (33) by the remanent insulating material (27, 35). This process is applicable to the GaAs/GaAlAs III-V material system as also other material systems. Transistor devices produced by this process may be either bipolar or field-effect type.

TECHNICAL FIELD

The present invention concerns improvements in or relating to processesfor the manufacture of III-V semiconductor devices--e.g. bipolar andfield-effect transistor devices. Especially, reference will be made togallium arsenide (GaAs)/gallium aluminium arsenide (GaAlAs)heterostructure bipolar transistors. Other III-V homostructure andheterostructure materials, however, will be mentioned as also otherdevice types.

BACKGROUND ART

The theoretical performance advantages of gallium arsenide(GaAs)/gallium aluminium arsenide (GaAlAs) III-V bipolar transistorsover their silicon counterparts are well known. At present, however,higher bipolar circuit speeds have been obtained for silicon devices.There is one reason for this discrepancy: highly advanced silicontechnology makes possible the fabrication of devices of extremely smallsize hitherto unattainable with current GaAs processes. In particular,the "Super Self-Aligned" process (Sakai T., et al., "Prospects of SSItechnology for high speed LSI", IEDM 1985, Tech. Dig., p18.) representsthe state of the art for silicon.

There are considerable obstacles to the realisation of such a process inGaAs; silicon has intrinsic advantages such as a native oxide, thepossibility of polycrystalline silicon overgrowth for extended contactsand impurity diffusion, and a common contact metallurgy for p-type andn-type regions. Published schemes for self-alignment of GaAs/GaAlAsbipolar devices (e.g. Asbeck P.M., "Heterojunction Bipolar Transistors",IEDM 1985, Short course: Digital III-V Device and Circuit Technology",course notes p114., and, Izawa T., et al., "AlGaAs/GaAs HeterojunctionBipolar Transistors", IEDM 1985, Tech. Dig., p328.) have suffered fromdifficulties involved in contacting the base layer due to the need toremove any parasitic GaAs/GaAs homojunction regions between emitter andbase. Achieving a low contact resistance to the emitter is alsoproblematic. Scaling to the dimensions typified by the self-alignedsilicon device (above) presents great problems in these schemes.

DISCLOSURE OF THE INVENTION

The present invention is intended as a remedy to the problems outlinedabove and provides a process suited for producing highly self-aligneddevices with small feature geometry, i.e. devices, comparable thus ingeometry and size to state-of-the-art silicon devices.

In accordance with this invention, thus, there is provided a process forthe manufacture of a III-V semiconductor device, this process includingthe steps of:

providing a III-V semiconductor structure;

forming, upon an exposed surface of this structure, a masking area ofinsulating material;

applying an etch to remove surplus material adjacent to the maskingarea;

forming upon the insulating material, the side of the structure exposedby the etch, and, the surface of the underlying material exposed by theetch, a further and conformal layer of insulating material;

applying an anisotropic etch to remove the insulating material coveringthe underlying material whilst leaving insulating material covering thetop and side aforesaid; growing a layer of lattice matched material uponthe surface of the underlying material thus exposed, the same to providea first extended contact region, the upper surface of this grown layerlying below the top of the structure aforesaid;

forming, upon the surface of the grown layer, a covering layer ofinsulating material; and,

forming a second extended contact region lying above the top of thestructure aforesaid.

In the manner aforesaid insulation is provided between the first andsecond extended contacts by means of overgrown insulating material.Also, insulation is afforded between the structure material aforesaidand the first extended contact by the sidewall insulating materialremaining following the anisotropic etch.

In the method aforesaid and in particular for bipolar transistormanufacture, the growth of the lattice matched material for extendedcontact formation may be preceded by masked implantation, this stepbeing essential to afford electrical continuity to a buried base layer,part of the structure.

The composition of the III-V semiconductor structure, insulatingmaterials and extended contact materials may be varied as appropriate,depending on device type and application. Alternatives will beconsidered in the description that follows.

BRIEF INTRODUCTION OF THE DRAWINGS

In the drawings accompanying this specification:

FIGS. 1 to 7 are cross-sections showing heterostructure geometry atsuccessive stages of a process applied in accord with the presentinvention, the same resulting in a bipolar transistor device;

FIG. 8 is a cross-section of a bipolar transistor produced accordingly;

FIG. 9 is a cross-section illustrating alternative steps employed forthe process above;

FIGS. 10, 11 and 12 show in plan view and in cross-section a bioplartransistor of modified design, and,

FIGS. 13 and 14 are cross-sections showing semiconductor structuregeometry at the start and the end of a process applied to themanufacture of a field effect transistor.

DESCRIPTION OF PREFERRED EMBODIMENTS

So that this invention may be better understood, embodiments of theinvention will now be described and reference will be made to theaccompanying drawings. The description that follows is given by way ofexample only.

The process described below permits the fabrication of all active areasand contacts to those areas of a transistor using a single masking step;a second mask defines the base-collector junction area with a singlealignment. The steps in device fabrication may be as follows (refer toattached drawings): The starting material structure for the process is aconventional GaAs/GaAlAs bipolar epitaxial heterostructure (a typicalconfiguration 1 is shown in FIG. 1). The starting structure 1 showncomprises a substrate 3 of crystalline semi-insulating gallium arsenidematerial bearing a succession of epitaxially grown layers arranged forproviding n-p-n vertical transistor structure. These comprise one ormore n-type collector layers 5, namely a dopant enriched (n++) layer 7and a lightly doped (n-) layer 9 both of gallium arsenide material.These layers 7, 9 are covered by a base layer 11 of dopant enrichedp-type (p+) gallium arsenide material graded to gallium aluminiumarsenide material uppermost. This is then followed by emitter layers 13,namely an n-type gallium aluminium arsenide layer 15 and a dopantenriched n-type (n++) gallium arsenide capping layer. (It is noted thatother structural arrangements could be used for example those forproviding p-n-p vertical transistor structure, as also more complexlayered structures, e.g. n-p-n-p; p-n-p-n; p-n-p-n-p-n and n-p-n-p-n-pas requisite for n-p-n and p-n-p complimentary transistor structures.)

This structure 1 is coated with silicon dioxide (silox) dielectric 19and a photolithograhic photoresist 21 masking step used to define afeature 23. This step determines the emitter width W of the finisheddevice. The silox 19 (with photoresist 21 still present) is then used asa mask to etch the epilayer structure 15, 17 down as far as the GaAlAsregion 15 of the emitter 13 (FIG. 2). A p-type ion implantation step canthen be carried out (masked by the photoresist 21) to form a contact 25to the base layer 11 (FIG. 3). In the structure, no GaAs contact layeris needed for the base 11 since no metallisation is to be applieddirectly; therefore no parasitic GaAs/GaAs homojunction is present.

After photoresist 21 removal the whole structure 1 is coated with silox27 once more. This layer 27 can serve as the encapsulant for annealingof the p-type implant 25. A second photoresist 29 masking step alignedto the etched mesa feature 23, is then applied and an isolating implant31 is used to define the base-collector junction area, width W' of thisarea being shown (FIG. 4). After photoresist 29 removal a highlyanisotropic reactive ion etching step will remove the silox 27 from thep-type GaAlAs 25 surface. The entire emitter 13 will remain coated; thesidewalls are not affected by the anisotropic etch and the top has adouble thickness of silox 19, 27 prior to etching.

The next step is crucial to device fabrication. The GaAs wafer 1 is putback into an epitaxial layer growth apparatus and a p-type GaAscontacting layer 33 grown for the base 11. With the correct growthconditions GaAs will not nucleate on the silox-coated 19, 27 emitter 13.To achieve isolation between emitter contacts and base contacts, a layer35 of semi-insulating material (typically GaAlAs) is overgrown on thep-layer 33. The structure then appears as shown in FIG. 5. After removalfrom the growth apparatus etching will remove the exposed silox layer 19on the emitter 13; a further epitaxial growth step is then used toproduce an n-type GaAs contacting layer 37 (FIG. 6).

At this point, the active areas of the transistor have been defined andit only remains to provide metallised contact to them. Although thedevice itself may be very small, the overgrown epitaxial layers 33, 37provide laterally extended contact areas making this a relatively simpletask. There are several options here; a possible sequence is outlined inthe next series of figures. After coating of the structure with ann-type contact metal 39, a photoresist mask 41 is applied and used tomask an etch defining the emitter contact (FIG. 7). The same mask mayremain in situ and further etching followed by evaporation of p-typecontact metal 43 will follow. After etching to the collector layer 5 toapply the remaining contact 45 an extremely compact structure (FIG. 8)is obtained.

This transistor structure can be scaled to extremely small dimensions.As outlined, the process involved one alignment step. A two-level resisttype of structure may be used to eliminate this requirement.

FIG. 9 illustrates such a structure formed from a single masking step.An upper level of resist 47 defines the isolating implant; after removalof this layer a second resist layer 49 defines the other features of thetransistor self-aligned to the isolation step. This represents theultimate in self-alignment; a single feature is employed and noalignment at all is required.

FIG. 8 is only one possible way in which the self-aligned structure maybe contacted. With a transistor on this size the operating current willbe small and it is likely that the resistance of the overgrown p-typelayer will be sufficiently small to enable it to carry the base currentwithout the need for a metal stripe. This enables an even smaller typeof structure to be fabricated. A suitable arrangement may be as shown inFIGS. 10, 11 and 12.

The process just described serves to provide ultrasmall geometryGaAs/GaAlAs bipolar devices and this is the immediate application. Useof this type of contacting technique is not limited to the bipolarstructure, however. Other materials and other devices may also profitfrom the extremely small geometries made possible by extendedcontacting.

The process may be adapted, for example, to the manufacture of III-Vhomostructure and heterostructure field effect transistor structures.This is illustrated in FIGS. 10 and 11. Here a semi-insulating galliumarsenide substrate 3 is provided having an epitaxially grownhigh-mobility undoped gallium arsenide layer 9 and a heavily-dopedlow-mobility gallium aluminium arsenide layer 15. In the initial stageof processing a mesa feature is formed as previously. The depth of themesa does not extend below the thickness of the gallium aluminiumarsenide layer 15. In the course of this process, n-type dopant has beenimplanted--see dopant regions 51, and n-type dopant enriched extendedcontacts 53 have been formed for the source and drain of this Schottkycontact 55 is also provided. A compact p-channel high-electron mobilitytransistor (HEMT) is thus produced. As above, isolation is provided bysidewall insulation 27 and overgrown insulation material 35.

Although the GaAs/GaAlAs materials system has been described as example,there is no reason why other semiconductors could not be used; forexample, devices could be fabricated for the InP/GaInAs materialssystem. It is also possible that a mixture of semiconductors could beemployed--for example, the p-type extended contact overgrown on theGaAlAs could be germanium rather than GaAs (germanium is a good latticematch). In this case, it would be possible to achieve lower contactlayer sheet resistance and contact resistivity. InAs or GaInAs are otheralternative materials for the contact layer to the GaAs layer.

The process as described above utilised a final n-type epitaxial growthfor emitter contacting; an alternative (at the expense of deviceperformance) could be realised if an ohmic contact metallisation stepwas performed at this point instead (or a refractory ohmic contactdeposited prior to extended p-contact growth). This could provide anintermediate structure useful in the progress towards full processimplementation with very high performance.

Other component materials of the process could alter; the dielectriccited here is silox but other dielectrics (e.g. aluminium oxide, siliconnitride) could equally well be used.

Epitaxial overgrowth of the emitter during the base contact layer growthis suppressed by the silox (or other dielectric) layer; it is possible,however, that this overgrowth could be tolerated provided it could laterbe removed. This might, for example, be achieved by the use of carefuletching of a planarising layer applied over the entire structure; theemitter, a raised feature, would be exposed first and the overlyinglayer could then be etched off.

An isolating implant is cited as the means to define base-collectorjunction area. Other methods are possible including etching, growth ofnative oxide, or possibly selective area epitaxial growth of thejunction during fabrication of the bipolar epilayer structure. Theisolating implant avoids difficulties associated with these techniquessuch as non-planarity of the surface and the need to isolate base andcollector. Since these obstacles may be overcome, alternative junctionarea definition schemes are not precluded from the general scope of thisinvention.

What I claim is:
 1. A process for the manufacture of a III-Vsemiconductor device, this process including the steps of:providing aIII-V semiconductor structure; forming, upon a selected area of anexposed surface of this structure, a masking layer of insulatingmaterial; applying an etch to remove material adjacent to the maskedselected area to define a step having a masked top surface, a sidewalland a lower surface; forming upon the insulating material, the sidewallof the step and, the lower surface of the step, a further and conformallayer of insulating material; applying an anisotropic etch to remove theinsulating material covering the lower surface of the step whilstleaving insulating material covering the top surface and side wall ofthe step; growing a layer of lattice matched material upon the lowersurface of the step, the same to provide a first extended contactregion, the upper surface of this grown layer lying below the topsurface of the step; forming, upon the surface of the grown layer, acovering layer of insulating material; removing insulating material toexpose the top surface of the step; and, forming a second extendedcontact region lying above and in contact with the top surface of thestep.
 2. A process, as claimed in claim 1, wherein the III-VSemiconductor structure is of gallium arsenide and gallium aluminiumarsenide materials.
 3. A process, as claimed in claim 2, wherein thestructure comprises the following layers:a semi-insulating substratelayer of gallium arsenide; followed by at least one layer of n-typegallium arsenide; followed by a layer of p-type gallium aluminiumarsenide; and, followed by at least one layer of n-type galliumarsenide.
 4. A process, as claimed in claim 3, wherein the firstextended contact region is of one of the conducting, doped, materials:gallium arsenide or germanium.
 5. A process, as claimed in either claims3 or 4, wherein the second extended contact region is of one of theconducting, doped, materials: gallium arsenide, indium arsenide, orgallium indium arsenide.
 6. A process, as claimed in any one of thepreceding claims, wherein the insulating material is chosen from thefollowing group of insulating materials: silicon oxide, silicon nitride,and aluminium oxide.
 7. A process as claimed in claim 2, wherein thestructure comprises the following layers:a substrate layer ofsemi-insulating gallium arsenide; followed by a layer of intrinsicgallium arsenide; and, followed by a layer of n-type gallium aluminiumarsenide.